1. Field of the Invention
The present invention relates generally to integrated circuits and to self-aligned silicidation structures used in fabricating integrated circuits. More particularly, the invention relates to self-aligned silicidation structures which include a first and second insulating layer and to methods of forming such self-aligned silicidation structures.
2. State of the Art
In a self-aligned silicidation (SALICIDE) process, it is often necessary to exclude the formation of silicides on specific regions of the silicon substrate in order to maintain a sufficient level of resistance. For example, it is desirable to prevent silicide formation on electrostatic discharge (ESD) diffusion areas of the device.
FIGS. 1(a)-(d) illustrates a process flow for forming a silicidation exclusion area according to a conventional process. As shown in FIG. 1(a), a semiconductor substrate 100 includes a polysilicon gate structure which includes polysilicon gate 102, gate oxide 104 and sidewall spacers 106. With reference to FIG. 1(b), an oxide layer 108 is first deposited across the semiconductor substrate 100. As illustrated in FIG. 1(c), photolithographic patterning is performed by photoresist coating, exposure and development steps, resulting in photoresist mask 110. Oxide layer 108 is then wet etched using a hydrofluoric acid (HF) solution or is anisotropically dry etched, as shown in FIG. 1(d). The post-etched oxide covers only those areas of the device on which the formation of silicide is to be prevented, i.e., the silicide exclusion region 112. The remaining oxide prevents reaction between metal and silicon in the subsequent SALICIDE process.
In the above-described process, it is critical that the deposited oxide be of sufficient thickness such that it is not entirely consumed during reaction with the metal. For if the oxide layer is totally consumed, interaction between the metal and underlying silicon will undesirably and necessarily result in silicide formation on the silicide exclusion area.
Under conditions typical for a titanium-based SALICIDE process, the silicide-exclusion oxide 108 must have a minimum thickness of about 500 .ANG. to prevent the entire consumption thereof. As shown in FIG. 1(d), while the oxide layer 108 may not be entirely consumed, both the shape and width of the sidewall spacers (dashed line is pre-etched spacer) and field oxides (not shown) in the unmasked areas may be altered during the HF wet etching or anisotropic dry etching step. In addition undercutting of the oxide beneath photoresist mask 110 may occur.
The features underlying oxide layer 108 are particularly susceptible to profile alteration when the oxide layer is thick, since the process requires a significant amount of overetch to clear the silicon areas requiring silicidation. Such modification of the underlying features, such as the spacer and field oxides, is particularly disadvantageous. Any change in the integrity thereof can adversely impact the device characteristics in addition to the subsequent SALICIDE process. Consequently, device yield can be significantly lowered if such modifications in feature profiles occur.